Academic Posters

Flip chip bonding is the most desirable direct chip attachment approach for minimizing electronic assembly size as well as improving device performance. For most prototyping applications it is not cost-effective to purchase individual integrated circuits (ICs) that are solder-bumped as this typically requires the purchase of entire wafer. Also, many unpackaged ICs in die form are not available for purchase as an entire wafer for subsequent solder bumping. As an alternative to solder bumping, manufacturers of wire bond equipment have developed the gold stud bump process which allows single ICs to be automatically bumped using 1-mil gold wire. However, the rapid formation of brittle aluminum-gold (Al-Au) intermetallics at elevated temperatures (>200oC) precludes the use of thermocompression flip chip bonding due to the unreliability of the bond at the IC pad interface. To overcome the intermetallic problem at the ICs aluminum-metallized bonding pads, an electroless nickel and gold plating process was developed for making a gold-bondable diffusion barrier for use on individual, unpackaged silicon ICs. This process provided an electroless gold layer suitable for accepting the gold wire stud bumps as well as providing the necessary barrier to Al-Au intermetallic formation. A number of experiments were conducted using electroless nickel of various phosphorus contents to determine which would provide an optimal diffusion layer. Data will be presented comparing immersion and autocatalytic gold plating processes. Test wafers were stud-bumped and exposed to accelerated temperatures then, shear tested. Electroless nickel, immersion and autocatalytic gold plating process parameters were optimized to provide high reliability interconnections when using the high temperature thermocompression flip-chip bonding die-attach method.

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Printed wiring board (PWB) delamination is an ongoing problem as complexity, layer count, soldering temperature, and soldering time increase. This issue is of even more importance because of ROHS requirements related to no-lead solders.

A sudden increase in delamination was observed in polyimide PWBs built to military specifications by JHU/APL during soldering operations for a spacecraft application. The delamination was first observed in a microsection of an 18 layer motherboard with two ounce inner layers that had been soldered using a vapor phase reflow process. The delamination was only at the inner layer laminate/ prepreg interfaces, not at the inner layer copper surfaces. Over the next few months the problem continued to appear randomly on a number of PWBs during assembly processes including hand soldering. All of these PWBs had passed Mil-PRF-55110 Group A tests and some had passed routine Group B testing including rework simulation. The problem was also observed on a PWB built at another facility.

JHU/APL's facility has manufactured PWBs for many years without observing this problem. It was apparent that the purchased material or a processing step(s) had changed. The problem was seen on material from various suppliers.

To understand the problem it was decided to manufacture 18 multilayer test panels. These test panels were built with different board material, inner layer treatments, mechanical scrub methods, and etch chemistries followed by soldering using various methods.

Results of tests on these panels will be presented that include chemical analysis, tensile testing, and microsectioning. A theory as to the cause will also be presented as well as a description of an additional quality check that is now being performed at JHU/APL on all military PWBs. In addition, some suggestions will be offered on how to process inner layers to prevent the problem from appearing and increase peel strengths.

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The Accelerated Thermal Cycling (ATC) test is time consuming and also often causes a bottle-neck in the lab loadings. As a result, mechanical stress tests, such as bend and shear tests, serves a substitute to shorten the cycling time. However, it deserves more detailed studies to understand which one is the best alternative of ATC test. Hence, the study conducts a series of bend and shear tests on the flip chip ball grid array (FCBGA) components designed with daisy chain circuits. Meanwhile, the theoretical mechanics analysis for thermal loading, and Finite Element Analysis (FEA) to model the bend, shear and thermal cycling tests are also performed. It is expected to find a mechanical stress test that can resemble the ATC test most based on the corresponding investigations on the failure cycles, failure modes, stress magnitudes and distributions, as well as the physics of the reliability tests. In the theoretical analysis, a simplified Suhir’s two-layer model is extended to a tri-layer beam model to simulate the component’s packaging structure. The relating interfacial normal and peeling stresses are evaluated. Besides, the FEA can provide an insight of the stress distributions on components under those tests for comparison purposes. Both leaded solder material with composition of 63Sn37Pb and unleaded solder with Sn3.0Ag0.5Cu, Sn4.0Ag0.5Cu, are used in the bend and shear tests. The study reveals that the magnitudes variations and distributions of thermal stresses on the FCBGA package, no matter from the theoretical or nonlinear FEA analyses, all indicates that mechanical shear fatigue test has good agreement with those from the ATC test. It is then concluded that cyclic shear test should be taken as the best alternative for the ATC test. However, based on the findings in the stressed states of components during the ATC test, the cyclic shear test has to include a short period of dwell at the two extreme of the stroke. With this improvement of the test, it will make the outcomes of mechanical stress test a step further be closer to that of ATC test.

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Dispersions containing nano-scaled metal particles were double-sided printed with vias on polyimide substrates using an x/y-plotter for the lateral movement of a piezo-electric print-head with 100 µm nozzle diameter. The plotter was controlled by a program written in HT-BASIC with HPGL-commands. This low-cost experimental setup allowed us to manufacture a FM radio as a demonstrator for highlighting the potential of the ink-jet technology for manufacturing electronic devices. The silver ink with a particle size of 5–10 nm was ink-jet printed to a thickness of 3–4 µm, 200–300 µm wide and subsequently annealed at temperatures between 150 and 300 oC for 120 to 10 minutes. At sufficient heat treatment conditions an electrical conductivity of the tracks of up to 40 percent of bulk silver was achieved. Though the microstructure of the silver tracks has not yet been investigated in detail, it could be shown that there is a strong correlation between the electrical conductivity and the micro-hardness of the annealed structures. The poster will display the experimental setup, the results of various printing, annealing and micro-hardness experiments as well as the FM radio which can also be enjoyed at http://www2.efi.fh-nuernberg.de/labs/me/me3/index.htm.

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In electronic packaging, nearly all semiconductor chips are bonded to copper (Cu) in the form of either Cu pads in flip chip configuration or bulk Cu substrate. Semiconductors and Cu, however, have a severe mismatch in coefficient of thermal expansion (CTE). Silicon (Si) has CTE of 2.7x10-6/oC and most III-V compound semiconductors have CTE ranging from 4x to 7x10-6/oC. These CTE values are much smaller than that of Cu, 17 x 10-6/oC [1]. It, thus, has been a challenge in electronic industries to produce a reliable metallic joint between chips and Cu substrates.

In this project, our objective is to bond Si chips to Cu substrates using metallic joints without any flux. To deal with the CTE mismatch, a 280μm thick silver (Ag) foil is first laminated on Cu substrate at 250 °C. Since Ag has relatively low yield strength, 1/3 of Sn3.5Ag solder and 1/10 of Cu [2], the Ag foil can incur and endure significant plastic strain at relatively low shear stress to accommodate the displacement changes caused by CTE mismatch. After laminating, 5μm indium (In) and 0.1μm Ag capping layer are electroplated over the laminated Ag. The thin Ag capping layer is used to prevent oxidation of inner In to achieve fluxless feature. On the Si chips, Cr and Au layers are deposited, and followed by electroplating 10μm Ag. The bonding process between Si/Cr/Au/Ag and Cu/Ag/In/Ag is performed at 205oC in 50 millitorr vacuum. The process is entirely flux-free. Nearly perfect joints are achieved. The resulting joints consist of three distinct layers: Ag, Ag2In, and Ag. A further annealing step can convert the Ag2In intermetallic compound (IMC) into solid solution phase (Ag) through solid-state reaction. Afterwards, the final joint contains only three layers, Ag, (Ag), and Ag. It has a melting temperature higher than 850 °C. Without any IMC layers inside joints, all reliability problems associated with IMCs and IMC growth do not exist anymore. After bonding, the laminated Ag on Cu substrate still has 250µm in pure Ag form. In the design, this Ag layer replaces a portion of the Cu substrate thickness. Since Ag has higher electrical conductivity and higher thermal conductivity than Cu, the use of laminated Ag layer improves the thermal performance of the packaged devices.

Here are the innovative features of this new bonding design and process:

1. Thick laminated Ag layer on Cu substrate to relive shear stress caused by CTE mismatch between Si and Cu through plastic deformation in Ag.
2. Thick laminated Ag layer on Cu substrate to replace a portion of the Cu substrate to improve thermal performance.
3. Fluxless bonding process between Si and laminated Ag using Ag-In system to produce joints that have melting temperature higher than 850 °C while the bonding process is performed at 250 °C.

[1] G. K. White, “Thermal expansion of reference materials: copper, silica, and silicon,” J. Phys. D: Appl. Phys., 6, pp. 2070-2078, 1973. [2] http://emat.eng.hmc.edu/.

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In the last few years, many new lead-free alloys have been proposed to improve drop test reliability of solder joints, for example, low Ag content SnAgCu alloys. The proliferation of new lead-free alloys presents a challenge to the assembly process. What should a reflow profile be for SAC305 BGA balls assembled with SAC105 paste, Sn3.5Ag paste, SnPb paste, or SnPbAg paste? What about SAC105 BGA/CSP balls? It is well known that incomplete mixing of solder paste and BGA/CSP solder balls would result in serious reliability risks. Therefore, it is of critical importance to understand the final alloy composition and the liquidus temperature of the final alloy composition in BGA/CSP assemblies. This poster presents detailed algorithm of calculating mixed alloy composition and its liquidus temperature for various BGA/CSP assemblies. The liquidus temperature of the mixed composition is the minimum solder joint temperature to achieve a sufficient amount of solder sphere collapse and a complete mixing with solder paste. An applet calculator has been developed and is available to use online at http://www.calpoly.edu/~pan/LTCalculator.html. After the information of the package, the stencil and the solder paste being input, the calculator will show the mixed final alloy composition (the percentage of Sn, Pb, Ag, and Cu in weight), the solder volume, and the estimated liquidus temperature of the final alloy. It is expected that the calculator will provide guidance for engineers to develop a reflow profile for various lead-free soldering assemblies.

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Recently, the authors succeeded in developing a room temperature wiring method for Ag nanoparticle paste. In this method, the Ag nanoparticles are coated with an alkylamine dispersant. In order to remove the alkylamine dispersant from printed Ag nanoparticle lines, the lines were simply dipped in methanol for a few seconds. By this treatment, the alkylamine dispersant could be easily removed and the nanoparticles sintered even at room temperature. The dodecylamine dispersant adsorbs to the Ag nanoparticles and protects them against aggregation or sintering. The Ag nanoparticles can maintain their initial shape over 150 days at 5 °C. However, once the Ag nanoparticles are dipped in methanol, the stably adsorbing dodecylamine is removed and dissolved into methanol. Bare Ag nanoparticles can be sintered and coarsened even at room temperature. Depending on the fact that the dispersant removal is controlled by dissolution of dodecylamine, other alcohols such as ethanol and isopropanol also have a great effect on achieving the room temperature sintering of printed Ag nanoparticle lines. It can be said that the solubility of dodecylamine in the treatment agents is one of the essential factors for the current technology. Ag nanoparticles are sintered and coarsened substantially by hot methanol even over a short time for seconds. Beyond 40 °C, the reaction becomes very fast. For instances, the coarsened Ag nanoparticles, over 30 nm in diameter, can be observed by methanol dipping only for 10 s at 40 °C. The resistivity treated at 40 °C for 30 s or at 60 °C for 10 s reaches in the order of 10-6 Ωm, and the behaviors of electrical resistivity correspond well to the Ag nanoparticle growth. It is also found that the sintering of Ag nanoparticles is not uniform. The coarsened Ag particles grow by absorbing surrounding small nanoparticles both at room temperature and at elevated temperature. The present work demonstrated the great potential of the alcohol dipping treatment for printed Ag nanoparticle lines for printed electronics. Since many organic devices and flexible printed circuit boards such as PET/PEN films are quite weak against heating, the room temperature processing with alcohols can provide much opportunity to the new electronics field.

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The spontaneous growth of surface defects, including whiskers and hillocks, on tin based electroplated films is believed to be a stress relief phenomenon. Previous research has shows that it is possible to plate pure tin and observe only hillock growth. Tin whisker growth, however, can be biased over hillock growth with the addition of copper contamination to the electrolyte. This increase in propensity to whisker is accompanied with an increase in plating stress and long-term stress, as measured using cantilever beam deflection. For this work, the addition of lead and copper to tin based electroplated films was evaluated. Films were plated at varying current densities and with varying amounts of lead and copper. Microstructure and surface defect characterization was performed using focused ion beam and SEM. Results from the analysis were used to build on a defect growth model considering the ratio between surface uplift to grain boundary motion.

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For decades, more than 90 percent of printed circuit boards (PCB) are based on fiberglass reinforced polymer composites. Today, the most successful and widely used resin systems for PCBs are epoxy resins, which is petroleum-based and non-renewable. Flame retardancy of PCBs has commonly been achieved by brominating the epoxy resin, which is still used in the overwhelming majority of materials. However, environmental and health concerns over brominated materials encouraged researchers to find alternative flame retardants. By far, E-glass is the most commonly used fiberglass for printed circuits. Unfortunately, the process of manufacturing woven fiberglass cloth begins with melting the various inorganic components, which requires a large amount of energy. To decrease environmental impact and health concerns, the ACRES group at the University of Delaware presented new bio-based composites from modified plant oil, halogen-free flame retardants and chicken feather fibers for printed circuit applications. Epoxidized soybean or linseed oils and different types of polycarboxylic anhydrides were used with presence of catalysts. Chicken feather fibers are all natural and these fibers are compatible with several modified plant oil resins. The hollow, light weight fibers innately contain a significant volume of air which made their dielectric constants lower than e-glass fibers. The feather fibers are tough to withstand both mechanical and thermal stress. Chicken feathers are abundant and cheap since the U.S. poultry industry generates more than one billion kilograms of feathers annually as byproducts. Alternatively, epoxidized plant oils were also functionalized with acrylate groups, guided by the newly developed Twinkling Fractal Theory. The halogen-free diethylphosphinic acid aluminium salt and/or melamine polyphosphate were added to the system as flame retardants. The bio-composites were optimized to meet the requirements of IPC 4101B specifications. IPC TM 650 test methods were adapted. The peel strength, dielectric properties, resistivity, flexural strength and flammability of the resultant materials met or were close to the requirements. The new bio-based PCBs from plant oils and chicken feathers, which potentially can replace the conventional FR-4 laminates, had much less carbon dioxide footprint and were more sustainable. This project was supported by the National Research Initiative of the USDA Cooperative State Research, Education and Extension Service, grant number 2005-35504-16137.

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The ceramic dielectric used in multilayer ceramic capacitors (MLCCs) is known to be susceptible to cracking in response to board flexure or thermal processing. Flexible termination capacitors were developed to reduce the transmission of stresses to the brittle ceramic and prevent cracking. Since their introduction there have been few published studies on the reliability of these capacitors under environmental stresses. A set of experiments was performed to compare the effects of termination type (standard vs. flexible), presence of a conformal coating (acrylic coating vs. no coating), and voltage bias level on the electrical parameters of precious metal electrode MLCCs when exposed to temperature-humidity-bias (THB) conditions. In-situ monitoring of capacitance, dissipation factor and insulation resistance allowed detection of changes in electrical parameters. For example, insulation resistance at 85 °C and 85 percent RH was two to three orders of magnitude lower than at room temperature and humidity. Both permanent and intermittent failures were observed. Flexible termination capacitors were found to have a greater number of permanent failures compared with standard termination capacitors, although most of these failures occurred at test durations greater than 1000 hours. The majority of these failures were also found to occur in the capacitors which were biased at the rated voltage. The conformal coating was found to have no significant effect on MLCC reliability. Failure analysis revealed that metal migration was the failure mechanism and produced a conductive path between two internal electrode layers.

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Development of lead-free solders with melting temperatures near traditional eutectic Pb/Sn solder is needed to limit damage to heat sensitive microelectronic components and devices. A possible method for reducing the melting temperature of Pb-free solders is by using nanoparticle solder pastes, in which the nanoparticles melt at temperatures far below their bulk counterparts due to the thermodynamic size effect. Particles with 5 nm diameters, observed to melt at temperatures below traditional Pb/Sn solder, are combined with flux (organic rosin used to prevent and remove oxide layers) to produce nanosolder pastes. The prototype nanosolder pastes display nanoparticle coalescence, in some cases to sizes with “bulk” melting temperatures, as characterized by differential scanning calorimetry (DSC).

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Under pressure from RoHS, microelectronics companies are exploring possible high temperature lead-free solders to replace the 95Pb-5Sn tin-lead alloy used for chip interconnects and hierarchical soldering processes. This study investigated a range of Bi-Ag binary eutectic alloys as suitable high temperature lead-free solders and as partially molten joining materials. Results will be presented describing the wetting of these alloys as a function of alloy composition, temperature, and flux type, their microstructures, and their resulting electrical and mechanical properties. Of greatest importance for use in interconnects is that, as the Ag concentration increases, the Ag dendritic primary phase provides not only a more electrically conductive path than high Bi alloys, but also improved mechanical properties.

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The aim of the work is development of cheap reliability testing methods, applicable for small producers of electronic equipment after implementation of ROHS and REACH directives. Methods and results of accelerated reliability tests by thermal and mechanical cycling of SnPb and lead-free solder joints are described. Thermal shock cycling method and mechanical method of cycling bending and warping of PCB samples with soldered SMT and BGA components are compared. Thermal shock cycling test was realized in two-zone climatic chamber. Mechanical cycling tests were realized on PC controlled test stand, developed in TU Warsaw. Charge factors applied by mechanical and thermal tests are compared. For stress and strain analysis were applied the FEM models. For obtaining of relative deformation ΔL between soldered component and PCB in mechanical test was applied the bending system exerting curvature C, moment M and other charge conditions, uniform for all components soldered on whole surface of the PCB sample. This system shows advantages comparing to known three - or four - point bending methods. The failures were detected by measuring of the joint resistance. Design and data of test specimens for simple resistance measurements and failures detection and relations between bending curvature of PCB sample and joint resistance are shown. The failure modes are classified. Influence of test parameters on failure distribution data and characteristic of joint parameters are discussed. The failure probability distributions on Weibull plots for mechanical and thermal cycling are compared. The failure rate values for early life failures of SnPb and lead – free joints are compared and practical conclusions for soldering processes and equipment are discussed. The investigations showed the possibility of simplified reliability assessment of lead-free electronic products by mechanical fatigue testing. Advantage of this method is lower cost and shorter test time than by thermal cycling. Mechanical cycling method by bending is proposed for standardization.

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As a result of the global transition to lead-free electronics, the majorities of the electronic component manufacturers are now using pure tin or tin-rich alloys for terminal and lead finishes. Tin whiskers have been one of the serious failure causes for electronics and aerospace equipments. Tin whiskers spontaneously grow from tin based lead-free finished surfaces even at room temperature. Comparing with pure tin plating, some tin alloy plating such as Sn-Bi was found to be rather immune to whisker formation. However, the mechanism of alloying effects on whisker growth is still unclear. In this study, growth behavior of tin whisker was examined on the various tin alloy platings under the various conditions. Furthermore, we propose a new approach to prevent the tin whisker by surface treatment, such as Ni, Au, Pd, on pure tin plating. Ni, Au and Pd layers with the thickness from 50nm to 200nm were deposited on matte tin plating by flash-coating process. Comparing with pure tin plating, metal layer/Sn plating samples significantly suppressed the Sn whisker formation under the room temperature, compressive stress, 55 °C/85 percent and 85 °C/85 percent relative humidity and thermal fatigue conditions.

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The spontaneous growth of surface defects, including whiskers and hillocks, on tin based electroplated films is believed to be a stress relief phenomenon. Previous research has shows that it is possible to plate pure tin and observe only hillock growth. Tin whisker growth, however, can be biased over hillock growth with the addition of copper contamination to the electrolyte. This increase in propensity to whisker is accompanied with an increase in plating stress and long-term stress, as measured using cantilever beam deflection. For this work, the addition of lead and copper to tin based electroplated films was evaluated. Films were plated at varying current densities and with varying amounts of lead and copper. Microstructure and surface defect characterization was performed using focused ion beam and SEM. Results from the analysis were used to build on a defect growth model considering the ratio between surface uplift to grain boundary motion.

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